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Backend Target and Master Dataflow Signals
Backend Target and Master Dataflow Signals
The signals in Table 5-3 are used for Target and Master data transfers between the core and the user’s backend logic. All
these inputs and outputs are synchronous to the PCI clock. Users should ensure that setup times are met across this
interface.
Table 5-3 · Dataflow Interface Signals
Name
Type
Width
Description
Active high bus indicating which BAR is being used for the current transaction. Values
'000' to '101' indicate BARs 0 to 5, '110' indicates the Expansion ROM, and '111'
BAR_SELECT
Output
3
indicates that no transaction is in progress. This output becomes valid on the same clock
cycle where DP_START is asserted and returns to '111' on the same clock cycle where
DP_DONE is asserted.
Active high signal indicating a read transaction from the backend. This output becomes
RD_CYC
Output
1
valid on the same clock cycle where DP_START is asserted and returns to 0 on the same
clock cycle where DP_DONE is asserted.
Active high signal indicating a write transaction from the backend. This output becomes
WR_CYC
Output
1
valid on the same clock cycle where DP_START is asserted and returns to 0 on the same
clock cycle where DP_DONE is asserted.
Active high signal indicating that the transfer is a 64-bit transfer. This output becomes
XFER_64BIT
Output
1
valid on the same clock cycle where DP_START is asserted and returns to 0 on the same
clock cycle where DP_DONE is asserted.
DP_START is an active high pulse indicating that a PCI transaction to the backend is
DP_START
Output
1
beginning. A DP_START will always be followed by a DP_DONE when the cycle
terminates.
Active high pulse indicating that a PCI transaction to the backend has finished.
DP_DONE
Output
1
DP_DONE pulses will also occur when the core is inactive at a time when other PCI
devices complete their PCI access cycles.
Active high read strobe indicating that the backend is ready to provide data to the core.
RD_STB_IN
Input
1
Data will only be transferred when both RD_STB_IN and RD_STB_OUT are active. If
the signal does not become active within the limits defined by the PCI bus, the read cycle
will be terminated and the PCI bus terminated with a disconnect without data.
Active high read strobe indicating that the core is ready to fetch data from the backend.
Data will only be read when both RD_STB_IN and RD_STB_OUT are active.
RD_STB_OUT
Output
1
The core will read data from the MEM_DATA_IN bus on the next rising clock edge, i.e.,
while the strobes are active if RD_SYNC is LOW, or on the following clock edge if
RD_SYNC is HIGH.
Active high input indicating that the backend is ready to receive data from the core. If the
WR_BE_RDY
Input
1
ready signal does not become active within the time limits defined by the PCI bus, a
disconnect without data will be initiated.
Active high output indicating that the data should be written to the backend device now.
WR_BE_NOW
Output
4/8
Four write strobes are provided for 32-bit cores, one per byte. For example,
WR_BE_NOW[0] indicates that data bits 7:0 should be written. 64-bit cores provide
eight write strobes, one per byte.
v4.0
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